Spatiotemporal Photonic Interleaving Network enables high-density optical convolutional processing for light-speed computing
https://www.eurekalert.org/news-releases/1138638 "chip-area optical processor bottleneck overcome routing light across recursive tree of cascaded shared wavelength domain delay segments... scalable, reconfigurable, reduces waveguide-length complexity... validated using 220-nm silicon-on-insulator chip operating at 49 GBd, processed handwritten digits with >0.98 optical-to-digital output agreement... enables multiple image-processing tasks/ configurable kernel geometries to share same core... signal processing projected to reach 29.7 trillion operations/ second"