P-type transistors fabricated using monolayer WSe₂ match n-type electron mobility, achieving perfectly balanced, ultra-thin CMOS chips
https://techxplore.com/news/2026-06-monolayer-wse-high-p-transistors.html "p-type 2D transistor development constrained by silicon scaling limits, including severe contact resistance/ lack of reliable chemical doping strategies, overcome utilizing monolayer tungsten diselenide integrated with interfacial doping technique optimizing electrical transport... minimizes structural contact resistance while boosting hole carrier mobility to match n-type thresholds, paving a clear engineering path for sub-nanometer logic chips that optimally balance processing speed with low power consumption"