Highly scalable sequential stacking of silicon layers vertically on a single die, extending Moore's law

https://matse.illinois.edu/news/85775

"stacking hindered by 400°C thermal limit preventing lower-level metal wire melting, overcome using roll laminator at 200°C transfering ultra-thin, freestanding single-crystalline silicon nanomembranes onto receiving wafer with 98–100% device yield... incorporate junctionless transistor architecture circumventing high-temperature chemical doping steps typically required... linked 3 stacked layers creating logic circuits/ static RAM... boosts data-intensive AI computing processing density/ speed"