Today's Tech News: Notable or Not?

https://www.eurekalert.org/news-releases/1144571 "MOSFETs conduct current both ways when on/ block voltage in 1 when off, requiring 2 side-by-side SiC chips... overcome integrating bi-directional voltage blocking/ current conduction at individual unit-cell level, significantly shrinking chip/ improving manufacturing yields...each unit cell incorporates integrated Schottky diode optimizing electrical conductivity/ blocking performance... renewable energy systems, high-voltage: matrix converters, current-source inverters, bi-directional EV chargers"

https://www.sciencealert.com/strange-material-gets-better-at-conducting-electricity-the-thinner-it-gets "both compared at 20 nm thickness... as copper microchip interconnects shrink, electrical resistance rises due to increased electron scattering at wire's surface (resistivity size effect)... overcome: single-crystal cobalt silicide, exhibiting lower resistance as get thinner, driven by quantum mechanical surface states facilitating smoother electron flow... maintain low signal loss up to 40 GHz/ remain thermally stable under high operational stress... viable replacement for copper in microchip manufacturing"

https://techxplore.com/news/2026-09-tracking-energy-reveals-voltage-pattern.html "discovered by mapping the real-time energy flow within electronic components... improves energy efficiency without requiring physical redesigns of existing chip architectures... practical pathway toward lower power consumption, reduced cooling demands, and greater operating stability in high-density electronics"

https://www.polyu.edu.hk/media/media-releases/2026/0831_polyu-develops-quantum-tunnelling-field-effect-transistor "semiconductor / AI computing hardware energy consumption constraints overcome using alternating 2D bismuth/ indium selenide layers fabricated via pulsed laser deposition... charge carriers tunnel quantum mechanically rather than relying on thermionic emission, enabling room-temperature operation using 160 (was 800) mV gate-voltage range... high: output current/ ON-OFF current ratio, needed to drive multiple downstream logic gates... scalable, CMOS fabrication compatible"

https://www.eurekalert.org/news-releases/1140970 "polarization superjunction gallium nitride microchip transistors built on low-cost silicon base withstand nearly 4 kV on tiny scale, 5X conventional limit.... leverages polarization, balancing negative/ positive charges internally, preventing localized electrical field building up... avoids temperature-sensitive chemical doping/ maintains low electrical resistance, reducing heat production/ energy loss... AI data centers, solar energy systems, EVs, consumer devices, grid infrastructure"

https://www.eurekalert.org/news-releases/1141169 "top-gate designs suffer from low controllability/ high electrical leakage at extreme temperatures... overcome adopting bottom-gate structure with well-based isolation, vastly improving threshold voltage control/ drastically suppressing leakage current... industry-standard manufacturing/ ion-implantation techniques, ensuring the design can be integrated into existing semiconductor fabrication processes... power electronics for harsh environments: aerospace, geothermal, industrial, defense"

https://www.eurekalert.org/news-releases/1140510 "prints up to 24 Pantoea agglomerans colonies on agar plates to create cell-based switches controlling production/ spatial flow of signaling molecules (instead of electric currents) to downstream components... combines 2 bacterial transistors with 3 relay strains... also performs demultiplexing... embeds autonomous computational control into living systems, such as coating agricultural crops to monitor pests and environmental conditions... demonstrated mathematical addition over eight-hour biological timescales" Related: Slime mold-inspired computing https://www.eurekalert.org/news-releases/1141335 MIT engineers connect bacteria to create living transistors https://news.mit.edu/2026/mit-engineers-connect-bacteria-to-create-living-transistors-0817

https://www.eurekalert.org/news-releases/1137988 "2D semiconductor-metal interfaces exhibit Fermi-level pinning/ high contact resistance, degrading dichalcogenides' carrier mobility, overcome establishing low-energy semimetallic contacts (bismuth/antimony)/ van der Waals integration forming Ohmic Schottky contacts without damaging atomic monolayers... <100 Ω μm contact resistance, maintaining thermal stability during standard back-end-of-line integration... field-effect transistors"

https://www.eurekalert.org/news-releases/1136831 "metrology tool for semiconductor foundries debugging yield/ current leakage in gate-all-around (eliminates current leakage/ short-channel effect) 2-layer chromium sulfur bromide van der Waals magnetic spin transistors, which combine logic switching/ non-volatile memory in 1 crystal... leverages space-charge-limited conduction dynamics, achieving 1M% electrical on/off ratio, 3K% magnetic on/off ratio... instant-on processors bypassing von Neumann memory bottleneck without interface losses"

https://phys.org/news/2026-07-nanoscale-gaps-reveal-atom-thin.html "maps design rules for atomic-scale, gap-controlled 2D materials... when 2D materials placed on slightly uneven metal electrodes, nanoscale gaps form at interface, altering distance electrons must cross... these gaps have greater impact on quantum tunneling/ unwanted electrical leakage creation than material's properties... practical guidance for engineers to control leakage currents, paving the way for smaller, more energy-efficient computer chips and ultra-thin memory devices"

https://www.eurekalert.org/news-releases/1135033 "p-type transistor... Volatile Surface Reconstruction: cesium-tin-iodide semiconductor layer potassium acetate treated forcing unstable defect-forming surface tin ion conversion to volatile compound evaporating under mild heat... simultaneously, vacated surface gaps filled with potassium iodide, forming self-protective passivation shield against ambient oxygen/ moisture... >50 cm^2/V field-effect hole mobility, >100 mn on/off current ratio, structurally stable at 100°}for >month... commercialization"

https://techxplore.com/news/2026-06-dog-bone-2d-nanoribbon-transistors.html "atomic scale rectangular nanoribbon transistors exhibit contact resistance where metal leads meet thin channel, degrading electrical current limiting performance... overcome widening contact regions at ends while keeping central channel ultra-narrow... maintains high-velocity carrier injection/ energy efficiency as post-silicon 2D semiconductor dimensions continue scaling downward under Moore's Law... enables carrying significantly higher current densities without experiencing typical miniaturization bottlenecks"

https://techxplore.com/news/2026-06-ibm-unveils-nanometer-chip-tech.html "nanostack 3D transistor architecture vertically layers/ staggers components... packs nearly 100 billion transistors onto fingernail-sized silicon, roughly doubling 2-nm node density... up to a 50 percent boost in computing performance or a 70 percent reduction in energy consumption... while the technology is currently an experimental research platform, IBM expects to see a viable path toward commercial mass production within the next five years"

https://techxplore.com/news/2026-06-power-kind-chip-human-brain.html "bypasses thermodynamic limits... microscopic sound vibrations controlling electrical charges movement within 2D materials... sound waves shift whether electrons/ holes dominate material's channel, reversing electrical current direction... multi-bit memory element prototypes vastly boost data storage density within a single cell... created the first surface acoustic wave -controlled artificial synapses, paving the way for highly efficient, biologically plausible AI hardware with expanded dynamic range... edge AI" Related: Reconfigurable AI device preserves long-term memory while acoustic waves reset short-term signals https://techxplore.com/news/2026-07-reconfigurable-ai-device-term-memory.html

https://techxplore.com/news/2026-06-monolayer-wse-high-p-transistors.html "p-type 2D transistor development constrained by silicon scaling limits, including severe contact resistance/ lack of reliable chemical doping strategies, overcome utilizing monolayer tungsten diselenide integrated with interfacial doping technique optimizing electrical transport... minimizes structural contact resistance while boosting hole carrier mobility to match n-type thresholds, paving a clear engineering path for sub-nanometer logic chips that optimally balance processing speed with low power consumption"

https://www.semiconductor-today.com/news_items/2026/jun/wolfspeed-090626.shtml "reducing conduction losses while raising heat thresholds optimizes mass-market EV drivetrain/ industrial power grid efficiency... enables more compact traction inverters (5x5 mm footprint), maximized current capability, improved durability (continuous junction temperatures up to 200°C while lowering overall switching losses)... world's first fully automated facility dedicated to cooking and processing larger 200 mm silicon carbide wafers using existing fabrication toolsets"

https://www.eurekalert.org/news-releases/1131038 "multi-functional organic transistor coupled with ultra-thin, charge-trapping polymer electret layer consolidates computing, non-volatile data retention, visual pixel illumination into single device... highly efficient/ ultra-compact: wearable electronics/ medical devices, advanced neuromorphic visual computing systems, flexible smart displays, neuromorphic hardware"

https://www.eurekalert.org/news-releases/1130440 "ultra-dense, sub-2nm transistors replacing silicon. making thin enough to suppress leakage current enlarges energy barrier, severely restricting electron flow... overcome using Raised Source and Drain structure, depositing additional tellurium to selectively thicken only areas directly in contact with metal electrodes... implemented using standard, low temperature large-area sputtering deposition... highly scalable/ commercially viable platform accelerating high-performance 3D microchip production"

https://www.eurekalert.org/news-releases/1129696 "thermal dissipation limited by chaotic photon scattering keeping microprocessors from running at sustained higher speeds, overcome using artificial atomic lattice synchronizing tailored structural vibrations into directed, fluid-like channels, with coordinated movement increases heat transport velocity, allowing up to 10X faster flow than in standard silicon substrates... advanced thermal management layer manufacturing... next-generation microchips and electric vehicle systems"

https://phys.org/news/2026-05-memory-transistors-bypass-boltzmann-limit.html "bypasses rule restricting energy efficiency/ down-scaling silicon chips, which at room temperature require a minimum voltage change to switch digital states due to thermal properties of electrons, forcing use of higher voltages... attempts to bypass relied on complex, material-specific ferroelectric layers/ quantum tunneling, overcome utilizing intrinsic non-equilibrium charge dynamics. enabling sub-thermal switching... microchip scaling, highly efficient, in-memory non-von Neumann high-density computing"