Atomic interface of 2D semiconductors engineered to significantly reduce contact resistance in sub-nanometer transistors

https://www.eurekalert.org/news-releases/1138925

"gate dielectric deposition involving monolayer molybdenum disulfide creates incomplete coverage/ electrical disorder impairing electron flow... overcome depositing ultrathin epitaxial aluminum layer directly on CVD-grown monolayer, selectively oxidizing forming 0.42-nm aluminum oxide buffer before applying high-kappa hafnium oxide dielectric... resulting top-gate transistors have equivalent oxide thickness near one nm/ high transconductance... wafer-scale sub-nanometer electronics"