Coating 2D semiconductors with 0.7-nm WS2 monolayer prevents structural degradation during subsequent dielectric isolation


"multi-nm multi-layer tantalum stack protective barriers/ liners for sub-20nm copper interconnect wires consume too much conductive area, degrading processing speed/ chip reliability... overcome using this monolayer preventing copper atoms from migrating into surrounding insulators while facilitating smooth, low-resistance metallic connection... staggered, labyrinth-like internal crystal grain orientation... 350°C atomic layer deposition across full wafers ensures compatibility with existing CMOS fabrication lines"

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https://www.eurekalert.org/news-releases/1132243

Engineering the next generation of semiconductor materials, one layer at a time

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