Combating fractional spurs in phase locked loops to improve wireless system performance in beyond 5G

https://techxplore.com/news/2024-02-combating-fractional-spurs-phase-loops.html

"minimizing fractional spur signals (reducing integrated PLL jitter from 243.5 to 143.7 fs) in fractional-N phase locked loops (PLLs) synthesizing, modulating, synchronizing oscillating signals for high-speed, error-free wireless data transceivers, radar... cascaded-fractional divider, splitting frequency control word, an internal PLL signal controlling output frequency, into 2 non-integer values... pseudo-differential digital-to-time converters improve power, delay range, noise, INLs naturally canceled... 65 nm CMOS"