Six stacks of semiconductors for hybrid CMOS microchips advances miniaturization for large-area electronics, toppling previous record of two

https://www.eurekalert.org/news-releases/1101744

"miniaturization crucial for flexible electronics, smart health, IoT, but current design approaches are reaching quantum mechanical limit/ skyrocketing cost, overcome using vertical stacking... fabrication mostly at room temperature, none beyond 150°C, so no damage to bottom layers as new layers added... layers' surfaces kept smoother, better aligned... scaling vertically: increasing functional density far beyond today's limits"

Related: Carbon nanotube 'sandpaper' polishes semiconductor surfaces down to a few atoms
https://phys.org/news/2026-02-carbon-nanotube-sandpaper-semiconductor-surfaces.html