Nanowire-based superconducting memory solves device size/ reliability trade-off for energy-efficient, fault-tolerant quantum computers

https://phys.org/news/2026-01-superconducting-nanowire-memory-array-significantly.html

"4 × 4 superconducting nanowire memory array overcomes bulk, using 1D nanostructures for scalable row–column operations, higher functional density (2.6 Mbit cm⁻²)... each memory cell: superconducting nanowire loop containing: 2 temperature-dependent switches changing resistance based on thermal pulses, variable kinetic inductor stabilizing electrical flow... magnetic flux data encoding... 10^−5 bit error rate... optimized write-/ read-pulse sequences minimizes bit errors/ maximizes operating margins"