Ten-stack, most to date, nanometer-thick metal oxide transistors, for compact and high density electronics

https://techxplore.com/news/2024-07-3d-metal-oxide-transistors-fabricate.html

"indium oxide layers on CMOS-compatible silicon/silicon dioxide substrates... in-between dielectric insulation layers of parylene-C... each layer patterned/ deposited at room temperature using 72 (instead of 10)-step lithography-based process... maximum field-effect mobility 15 cm2/V-1s-1, subthreshold slope 0.4 V/dec-1, current on/off ratio up to 108... low thermal budget, low interfacial roughness, faster switching speeds, lower power consumption, improved overall performance, compatible with existing manufacturing"