Intel introduces approach to boost power efficiency, reliability of packaged chiplet ecosystems

https://techxplore.com/news/2024-03-intel-approach-boost-power-efficiency.html

"new architectures and specifications for systems with multiple packaged chiplets... reducing circuits' frequencies enables order magnitude lower power/ bit and order or 2 more performance... getting more wires between 2 chiplets as bump pitch (minimum distance between bumps that will connect 2 chiplets) reduces usually increases frequency but UCIe-aligned technologies benefit from reduction in frequency, instead... this frequency reduction improves systems' power efficiency"